Programmable logic devices, such as a complex programmable logic device (CPLD) or a field programmable gate array (FPGA), may utilize a combination of non-volatile and volatile memory to deliver a single-chip solution supporting rapid start-up (often referred to as “instant-on” capability) and infinite re-configurability. The non-volatile memory (e.g., flash memory cells) within the non-volatile PLD stores the device configuration, with the PLD configured upon power-up by transferring the configuration data from the non-volatile memory to the volatile memory (e.g., configuration SRAM cells).
During the configuration data transfer from non-volatile to volatile memory, however, it is possible for the configuration data to be corrupted. If the configuration data is corrupted, the PLD may not function properly and device contention or damage may occur to the PLD or to external devices controlled by the PLD.
A conventional approach uses software to read out from the PLD the configuration data from the volatile memory to compare to the intended bit pattern to confirm that the programming was successful. This approach is time consuming and costly, for example, in terms of the software and on-board microprocessor that may be required to perform the verification. As a result, there is a need for improved programming verification techniques for non-volatile PLDs.